1. Field of the Invention
This invention relates to transistors coupled in series and/or in parallel to form a logic gate and, more particularly, to a more accurate method for forming ultra-small gate conductors for each of the transistors.
2. Description of the Related Art
Fabrication of a metal-oxide semiconductor (xe2x80x9cMOSxe2x80x9d) transistor is well known. The manufacture of an MOS transistor begins by defining active areas where the transistor will be formed. The active areas are isolated from other areas on the semiconductor substrate by various isolation structures formed upon and within the substrate. Isolation structures come in many forms. For example, the isolation structures can be formed by etching trenches into the substrate and then filling the trenches with a dielectric fill material. Isolation structures may also be formed by locally oxidizing the silicon substrate using the well recognized LOCOS technique.
Once the isolation structures are defined between transistor active areas, a gate dielectric is formed. Typically, the gate dielectric is formed by thermal oxidation of the silicon substrate. Thermal oxidation is achieved by subjecting the substrate to an oxygen-bearing, heated ambient in, for example, an oxidation furnace or a rapid thermal annealer (xe2x80x9cRTAxe2x80x9d). A gate conductor material is then deposited across the entire dielectric-overed substrate. The gate conductor material is preferably polycrystalline silicon, or polysilicon. The polysilicon layer is then patterned using a photolithography mask. The mask allows select removal of a light-sensitive material deposited entirely across the polysilicon. The material which is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed. Selective polymerization is often referred to as the xe2x80x9cdevelopxe2x80x9d stage of lithography. The regions which are non-polymerized are removed using the etch stage of lithography.
A typical n-channel MOS (xe2x80x9cNMOSxe2x80x9d) transistor employs n-type dopants placed into a p-type substrate. Conversely, a typical p-channel MOS (xe2x80x9cPMOSxe2x80x9d) transistor comprises p-type dopants placed into an n-type substrate. The substrate is generally a single crystalline silicon structure. Regions of the substrate which receive dopants on opposite sides of the gate conductor are generally referred to as junction regions, and the distance between junction regions is typically referred to as the physical channel length. After implantation and subsequent diffusion of the junction regions, the distance between the junction regions becomes less than the physical channel length and is often referred to as the effective channel length (xe2x80x9cLeffxe2x80x9d). In high density designs, not only does the physical channel length become small, so too must the Leff. As Leff decreases below approximately 1.0 xcexcm, for example, a problem known as short channel effects (xe2x80x9cSCExe2x80x9d) becomes predominant.
Integrated circuits designed with relatively small physical channel lengths in densely patterned circuit areas require careful attention be directed to the mechanism by which the gate conductor is formed. For example, if a set of gate conductors within a densely patterned area become too small, then SCE will be predominant for those transistors. It might be that the small Leff transistors will prematurely turn on or will incur sub-threshold currents, more so than the other transistorsxe2x80x94even though all transistors were designed to have the same physical channel length.
Slight variations in gate conductor length (i.e., physical channel length) even though not intentional may drastically alter the performance of a circuit design with relatively small physical channel lengths. This problem is significant in areas of densely patterned gate conductors such as, for example, logic areas containing numerous interconnected NAND and NOR gates. While it is desired that the series-connected and parallel-connected transistors within each logic gate be closely spaced to one another, it is equally desired that those transistors maintain a consistent channel length amongst themselves. If, for example, Leff of one parallel-connected transistor differs from that of the other parallel-connected transistor, then uneven turn-on transience may occur across the parallel connection.
The conventional lithography used to pattern closely spaced gate conductors (e.g., gate conductors of series-connected and parallel-connected transistors) suffers many drawbacks. For example, selective exposure is highly dependent upon accurately placing light on the light-sensitive material. Furthermore, light-sensitive material must consistently respond to the light with fine-line resolution. Any elevational disparity on which the polysilicon resides will result in slight changes in the point at which the light impinges on the light-sensitive material. This results in a variation in the polymerized/non-polymerized boundary.
It is therefore desirable to produce gate conductors which have an extremely small physical channel length to achieve high density logic cells. Although small in physical channel length, the desired gate conductors must be of consistent size across a somewhat elevationally disparate topography. In order to accurately produce a small gate conductor, a process must be used which avoids lithographic limitations of exposure, develop and etch cycles used in defining conventional gate conductors upon a gate dielectric. In order for a transistor which employs a relatively small gate conductor to achieve commercial success, improvements must be undertaken not only to the lithography procedure but also possibly to the junction itself. It may be necessary to incorporate a lightly doped drain (xe2x80x9cLDDxe2x80x9d) region at the interface between the junction and the channel area underlying the gate conductor. As Leff decreases commensurate with gate conductor size, LDD implants must be carefully controlled so as not to encroach into the relatively short channel while at the same time source/drain implants formed within the junctions must be sufficiently concentrated to minimize hot carrier effects (xe2x80x9cHCFxe2x80x9d).
The problems outlined above are in large part solved by an improved transistor configuration hereof. The improved transistor can be either a p-channel or an n-channel transistor. Importantly, p-channel transistors can be incorporated with n-channel transistors to form a logic gate. The logic gate comprises series-connected and parallel-connected transistors closely spaced and connected to form, for example, one or more NAND gates or NOR logic gates.
In regions where logic gates are prevalent, closely spaced transistors are needed having relatively short physical channel lengths. To define an ultra short physical channel length which maintains its effective consistency for each transistor across one or more logic gates, the gate conductors of those transistors are beneficially formed outside the conventional lithography process. Instead of depositing a gate conductor material across an entire planar surface, the present process employs a gate conductor material formed so that it is bounded on one lateral surface against a sacrificial structure. The bounded gate conductor can be formed by depositing a layer of polysilicon across and adjacent to the sacrificial structure. The gate conductor layer is then partially removed using an anisotropic etch technique, leaving a gate conductor which abuts the sacrificial structure. The height of the sacrificial material and the deposition thickness of the gate conductor material will define the entire gate conductor geometry.
According to one embodiment, spacers can be formed on opposed lateral surfaces of the gate conductor. The spacer on one lateral surface can be of dissimilar thickness than the spacer on the opposing lateral surface. Of benefit is the asymmetrical design of the ensuing transistor, wherein the drain-side spacer can be made thicker than the source-side spacer. Since the spacers define source/drain implant alignment, dissimilar spacer thicknesses will cause the drain implant area to be spaced farther away from the gate conductor than that of the source implant area.
The sacrificial material is patterned at a specific location upon a dielectric-covered semiconductor substrate. The material is sacrificial in that it later is purposefully removed from the dielectric-covered topography. The sacrificial structure includes a pair of opposed sidewall surfaces. Those sidewall surfaces serve as receptors against which a gate conductor is later formed. The sacrificial material is patterned such that it may reside over what will be a shared junction. Subsequent to forming gate conductors on opposed sidewall surfaces of a sacrificial material, and removing the sacrificial material, a dopant is placed in the region beneath where the sacrificial material once resided. The dopant is common to either the source or drain junction of the pair of transistors formed on opposing sidewall surfaces. Accordingly, each patterned, sacrificial material defines a mutual junction and a pair of gate conductors within a series-connected or a parallel-connected pair of transistors.
Gate conductors are formed by preferably depositing a polysilicon material across the upper and sidewall surfaces of the patterned, sacrificial material. An anisotropic etch, according to a preferred embodiment, comprises an ion-directed or ion-assisted plasma etch. The anisotropic etch is used to remove the polysilicon horizontal surfaces faster than polysilicon vertical surfaces. After the horizontal surfaces are completely removed from the sacrificial material and from the semiconductor topography a spaced distance from the sacrificial material, what remains is a gate conductor on the sidewall surfaces immediately adjacent the substantially vertical sidewall surfaces of the sacrificial material. The height of the gate conductor is dependent upon the height of the sacrificial material, whereas the thickness (or width) of the gate conductor measured from the sacrificial structure sidewall surfaces is dependent on the polysilicon deposition thickness as well as the anisotropic etch composition and duration. If the deposition thickness is quite large and the etch is minimal, the gate conductor can have a width which is relatively large. That width, which defines a channel length or Leff, is commensurately large.
Of prime importance is the avoidance of using conventional lithography to define physical channel length, or gate width. Instead, the present process uses lithography only to define an edge (i.e., sacrificial structure sidewall surface) of the gate conductor. Deposition and blanket anisotropic etch back is thereafter used to define the other edge of the gate conductor. Accordingly, the present gate conductors are configured using a combination of lithography and deposition techniques. The deposition can be performed at a slow rate so as to more carefully control, with fine-line resolution, the overall width of the ensuing gate conductor.
Broadly speaking, the present invention contemplates a logic gate. The logic gate is formed having a pair of closely spaced transistors which will be connected either in series or in parallel. Importantly, the spacing between transistors, and specifically, the spacing between transistor gate conductors is determined by the width between sidewall surfaces of a patterned sacrificial material.
According to one embodiment, a pair of sacrificial structures are formed by patterning a layer of sacrificial material. The sacrificial structures are spaced from each other upon the gate dielectric. Each of the pair of sacrificial structures includes a pair of opposed sidewall surfaces. A first pair of gate conductors extends across the gate dielectric laterally from the sidewall surfaces of one of the pair of sacrificial structures. A second pair of gate conductors extends across the gate dielectric laterally from sidewall surfaces of another of the pair of sacrificial structures. A first set of four implant areas are formed a spaced distance from each other within the semiconductor substrate after removal of one of the pair of sacrificial structures. The first set of implant areas are aligned with opposing edges of the first pair of gate conductors. Beneficially, two of the four implant areas of the first set may be shared as a contiguous junction area between the first p air of gate conductors. A second set of four implant areas may also be formed a spaced distance from each other within the semiconductor substrate after removal of another of the pair of sacrificial structures. The second set of implant areas are aligned with opposing edges of the second pair of gate conductors, wherein two of the four implant areas of the second set of implant areas may be formed contiguous with one another similar to contiguous implants of the first set of four implant areas.
The present invention further contemplates a method for forming a logic gate. The method comprises patterning a sacrificial material to form first and second sacrificial structures. The first and second sacrificial structures comprise a first pair and a second pair of opposed sidewall surfaces, respectively, extending substantially perpendicular from a dielectric-covered semiconductor substrate. A gate conductor is deposited across the first and second sacrificial structures. The gate conductor material can then be removed except immediately adjacent the first pair and the second pair of opposed sidewall surfaces. What remains is a first pair of gate conductors and a second pair of gate conductors extending from the first and second pairs of opposed sidewall surfaces, respectively. A first dopant is then implanted into the semiconductor substrate in alignment with the lateral surface of the first pair of gate conductors while a second dopant is implanted into the semiconductor substrate in alignment with a lateral surface of the second pair of gate conductors. The first dopant may be of opposite impurity type than the second dopant. An interlevel dielectric may be formed upon t he first and second pairs of gate conductors. Openings may be patterned through the interlevel dielectric and interconnect arranged upon the interlevel dielectric to form, e.g., a series-connected pair of n-channel transistors and a parallel-connected pair of p-channel transistors. Alternatively, the interconnect can be patterned to form a series-connected pair of p-channel transistors and a parallel-connected pair of n-channel transistors. In the former instance, a NAND gate can occur while in the latter instance a NOR gate can occur.